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NT7704
240 Output LCD Segment/Common Driver
Features
(Segment mode) ! Shift Clock frequency: 20 MHz (Max.) (VDD = 5 V 10%) 12 MHz (Max.) (VDD = 2.5V - 4.5V) ! Adopts a data bus system ! 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin ! Automatic transfer function with an enable signal ! Automatic counting function when in "chip select" mode, which causes the internal clock to be stopped by automatically counting 240 bits of input data (Common mode) ! Shift clock frequency : 4.0 MHz (Max.) ! Built-in 240-bits bidirectional shift register (divisible into 120-bits x 2) ! Available in a single mode (240-bits shift register) or in a dual mode(120-bits shift register x 2) 1. Y1 Y240 Single mode 2. Y240 Y1 Single mode 3. Y1 Y120, Y121 Y240 Dual mode 4. Y240 Y121, Y120 Y1 Dual mode The above 4 shift directions are pin-selectable (Both for segment mode and common mode) ! ! ! ! ! ! ! Supply voltage for LCD driver: 15.0 to 30.0 V Number of LCD driver outputs: 240 Low output impedance Low power consumption Supply voltage for the logic system: +2.5 to +5.5 V COMS process Package: Gold bump die / 272 Pin TCP(Tape Carrier Package) ! Not designed or rated as radiation hardened
General Description
The NT7704 is a 240-bit output segment/common driver LSI suitable for driving large scale dot matrix LCD panels used by PDA's, personal computers and work stations for example. Through the use of COG technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The NT7704 is good as both a segment driver and as a common driver, and a low power consuming, highprecision LCD panel display can be assembled using the NT7704. In the segment mode, the data input is selected as 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In the common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable.
Pin Configuration
D U M M Y Y 2 4 0 Y 2 3 9 Y 2 3 8 Y 2 3 7 Y 2 3 6 Y 1 2 3 Y 1 2 2 Y 1 2 1 Y 1 2 0 Y 1 1 9 Y 1 1 8 Y 5 Y 4 Y 3 Y 2 Y 1 D U M M Y
272 271 270 269 268
155 154 153 152 151 150
37 36 35 34 33
NT7704
1
2
3 V 1 2 L
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DVV U00 MLL M Y
VVVVSEDDDDDDDDXDLEF LMNVNVVVVVD 45SD / I 01234567C I P IR / DCSC54100U R32RRM R S O 3LSDCO KS M RR 1 2 L P Y O F F
1
V1.0
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NT7704
Pad Configuration
432 x x 225 x x
433
224
NT7704
448 x 1
ALK_L
Dummy Pad
x
ALK_R
209 x
208
Block Diagram
V0R V12R V43R V5R Y1 Y2 Y239 Y240
FR Level Shifter
DISPOFF
V5L
240 Bits 4 Level Driver
/240
V43L V12L
240 Bits Level Shifter
EIO1 Active Control EIO2
/16 /16 /16 /16 /16 /240
V0L
240 Bits Line Latch/Shift Register
LP XCK
8Bits2 Data Latch Control Logic
Data Latch Control
L/R MD S/C
/8
SP Conversion & Data Control (4 to 8 or 8 to 8)
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VSS VSS
2
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NT7704
Pad Description
Pad No. 1 - 12 13 - 20 21 -28 29 - 40 41 - 66 67 - 92 93 - 94 95 - 97 98, 99, 100 116, 117, 118 119 - 121 122 - 124 125 - 127 128 - 130 131 - 133 134 - 136 137 - 139 140 - 142 143 - 168 169 - 180 181 - 188 189 - 196 197 - 208 209 - 448 Designation V0L V12L V43L V5L VSS VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR L/R MD VSS V5R V43R V12R V0R Y1 - Y240 I/O P P P P P P I I/O I I I I I I/O I I I P P P P P O Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these pads must be connected to each other Power supply for the logic system (+2.5 to +5.5V) Segment mode/common mode selection Input/output for chip select or data of the shift register Display data input for segment mode Display data input for Segment mode/ Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input/shift clock input for the shift register Input/output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Display data shift direction selection Mode selection input Ground (0V), these pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output Description
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NT7704
Input / Output Circuits
VDD
I
Input Signal
Applicable Pins L/R, S/C, D0 - D6, DISPOFF , LP, FR, MD
VSS
Input Circuit (1)
VDD
I Control Signal
Input Signal
Applicable Pins D7, XCK
VSS
VSS
Input Circuit (2)
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VDD
Input Signal Control Signal
VSS
VDD
VSS
Output Signal
I/O
Control Signal
VSS
Applicable Pins EIO1, EIO2
Input / Output Circuit
V0
V12
Control Signal 1 O Control Signal 3
Control Signal 2
Control Signal 4
Applicable Pins Y1 to Y240
V43 VSS V5
LCD Driver Output circuit
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NT7704
Pad Description
Segment mode Symbol VDD VSS VOR, VOL V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects from +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias " Normally, the bias voltage used is set by a resistor divider " Ensure that the voltages are set such that VSS V5 < V43 < V12 < V0 " To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y240, externally connect ViR and ViL (I = 0, 12, 43, 5) Input pin for display data " In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD " In 8-bit parallel input mode, input data into the 8 pins D0 - D Clock input pin for taking display data " Data is read on the falling edge of the clock pulse Latch pulse input pin for display data " Data is latched on the falling edge of the clock pulse Direction selection pin for reading display data " When set to VSS level "L", data is read sequentially from Y240 to Y1 " When set to VDD level "H", data is read sequentially from Y1 to Y240 Control input pin for output deselect level " The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the LCD driver circuit. " When set to VSS level "L", the LCD driver output pins (Y1-Y240) are set to level V5 DISPOFF " When DISPOFF is set to "L", the contents of the line latch are reset, but the display data in the data latch are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge of the LP. At that time, if the DISPOFF removal time can not keep regulation with what is shown on the AC characteristics, then it can not output the reading data correctly. AC signal input for LCD driving waveform " The input signal is level-shifted from the logic voltage level to the driver voltage level and controls the LCD driver circuit. " It normally inputs a frame inversion signal The LCD driver output pin's output voltage level can be set to the line latch output signal and the FR signal Mode selection pin " When set to VSS level "L", 8-bit parallel input mode is set " When set to VDD level "H", 4-bit parallel input mode is set
D0 - D7
XCK LP
L/R
FR
MD
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Segment mode continued Symbol S/C Function Segment mode/common mode selection pin " When set to VDD level "H", segment mode is set " When set to VSS level "L", common mode is set Input/output pin for chip selection " When L/R input is at VSS level "L", EIO1 is set for output, and EIO2 is set for input " When L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output " During output, it is set to "H" while LP* XCK is "H" and then after 240-bits of data have been read, it is set to "L" for one cycle (from falling edge to falling edge of XCK), after which it returns to "H" " During input, after the LP signal is input, the chip is selected while EI is set to "L". After 240-bits of data have been read, the chip is deselected LCD driver output pins These correspond directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output
EIO1, EIO2
Y1 - Y240
Common mode Symbol VDD VSS V0R, V0L V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias. " Normally, the bias voltage used is set by a resistor divider " Ensure the voltages are set such that VSS V5 EIO1
EIO2
LP
L/R
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Common mode continued Symbol DISPOFF Function Control input pin for output deselect level " The input signal is level-shifted from the logic voltage level to the LCD driver voltage level, and controls the LCD driver circuit " When set to VSS level "L", the LCD driver output pins (Y1-Y240) are set to level V5 " While set to "L", the contents of the shift resister are reset and are not reading data. When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V43), and the shift data is read on the falling edge of the LP. At that time, if the DISPOFF removal time can not keep regulation with what is shown on the AC characteristics, the shift data is not read correctly FR AC signal input for LCD driving waveform " The input signal is level-shifted from logic voltage level to the LCD driver voltage level, and it controls the LCD driver circuit " Normally, it inputs a frame inversion signal The LCD driver output pin's output voltage level can be set using the shift register output signal and the FR signal Mode selection pin " When set to VSS level "L", Single Mode operation is selected. When set to VDD level "H", Dual Mode operation is selected Dual Mode data input pin " According to the data shift direction of the data shift register, data can be input starting from the 121st bit When the chip is used in Dual Mode, D7 will be pulled-down When the chip is used in Single Mode, D7 won't be pulled-down Segment mode/common mode selection pin " When set to VSS level "L", common mode is set Not used " Connect D0-D6 to VSS or VDD. Avoid floating Not used " XCK is pull-down in common mode, so connect to VSS or leave open LCD driver output pins " These correspond directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and output
MD
D7
S/C D0 - D6 XCK Y1 - Y240
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Functional Description
1. Block description 1.1 Active Control In segment mode, it controls the selection or deselection of the chip. Following a LP signal input, and after the select signal is input, a select signal is generated internally until 240 bits of data have been read in. Once data input has been completed, a select signal for cascade connection is output, and the chip is deselected. In common mode, it controls the input/output data of the bidirectional pins. 1.2. SP Conversion & Data Control In segment mode, it keeps input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. 1.3. Data Latch Control In segment mode, it selects the state of the data latch, which reads in the data bus signals. The shift direction is controlled by the control logic and for every 16 bits of data read in, the selection signal shifts one bit, based on the state of the control circuit. 1.4. Data Latch In segment mode, it latches the data on the data bus. The latched state of each LCD driver output pin is controlled by the control logic and the data latch control. 240 bits of data are read in 20 sets of 8 bits. 1.5. Line Latch/Shift Register In segment mode, it ensures all 240 bits which have been read into the data latch, are simultaneously latched on to the falling edge of the LP signal, and output to the level shift block. In common mode, it shifts data from the data input pin on to the falling edge of the LP signal. 1.6. Level Shifter It ensures the logic voltage signal is level-shifted to the LCD driver voltage level, and output to the driver block. 1.7. 4-Level Driver It drives the LCD driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, V5) based on the S/C, FR and DISPOFF signals. 1.8. Control Logic Controls the operation of each block. In segment mode, when an LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled, 240 bits of data are read in, and the chip is deselected. In common mode, it controls the direction of data shift.
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2. LCD Driver Output Voltage Level The relationship between the data bus signal, AC converted signal FR and LCD driver output voltage is as shown in the table below: 2.1. Segment Mode FR L L H H X Latch Data L H L H X DISPOFF H H H H L Driver Output Voltage Level (Y1 - Y240) V43 V5 V12 V0 V5
Here, VSS V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care 2.2. Common Mode FR L L H H X Latch Data L H L H X DISPOFF H H H H L Driver Output Voltage Level (Y1 - Y240) V43 V0 V12 V5 V5
Here, VSS V5 < V43 < V12 < V0, H: VDD (+2.5 to +5.5V), L: VSS (0V), X: Don't care Note: There are two kinds of power supply (logic level voltage, LCD driver voltage) for the LCD driver. Please supply regular voltage which is assigned by specification for each power pin. That time "Don't care" should be fixed to "H" or "L", avoiding floating.
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3. Relationship between the Display Data and Driver Output pins 3.1. Segment Mode: (a) 4-bit Parallel Mode MD L/R EIO1 EIO2 Data Input D0 H L Output Input D1 D2 D3 D0 H H Input Output D1 D2 D3 (b) 8-bit Parallel Mode MD L/R EIO1 EIO2 Data Input D0 D1 D2 L L Output Input D3 D4 D5 D6 D7 D0 D1 D2 L H Input Output D3 D4 D5 D6 D7 Number of Clock 30clock Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 29clock Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y232 Y231 Y230 Y229 Y228 Y227 Y226 Y225 28clcok Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y224 Y223 Y222 Y221 Y220 Y219 Y218 Y217 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 3clock Y217 Y218 Y219 Y220 Y221 Y222 Y223 Y224 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17 2clock Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 1clock Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Number of Clock 60clock Y1 Y2 Y3 Y4 Y240 Y239 Y238 Y237 59clock Y5 Y6 Y7 Y8 Y236 Y235 Y234 Y233 58clcok Y9 Y10 Y11 Y12 Y232 Y231 Y230 Y229 ~ ~ ~ ~ ~ ~ ~ ~ ~ 3clock Y229 Y230 Y231 Y232 Y12 Y11 Y10 Y9 2clock Y233 Y234 Y235 Y236 Y8 Y7 Y6 Y5 1clock Y237 Y238 Y239 Y240 Y4 Y3 Y2 Y1
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3.2. Common Mode MD L (Single) L/R L (shift to left) H (shift to right) L (shift to left) H (Dual) H (shift to right) Data Transfer Direction Y240 to Y1 Y1 to Y240 Y240 to Y121 Y120 to Y1 Y1 to Y120 Y121 to Y240 EIO1 Output Input Output Input EIO2 Input Output Input Output D7 X X Input Input
Here, L: VSS (0V), H: VDD (+2.5V to +5.5V), X: Don't care Note: "Don't care" should be fixed to "H" or "L", avoiding floating.
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4. Connection Examples of Segment Drivers 4.1. Case of L/R = "L"
first data (data taking flow) Y240 ----------------------->Y1 Y240 ---------------------->Y1 Y240 ---------------------->Y1 last data
EIO2
EIO1 L/R D0 - D7
EIO2
EIO1 L/R D0 - D7
EIO2
EIO1 L/R D0 - D7
XCK
XCK
XCK
MD
MD
MD
FR
FR
XCK LP MD FR D0 - D7 VSS /8
4.2. Case of L/R = "H"
VDD D0 - D7 FR MD LP XCK /8
XCK
XCK
FR
LP
LP
LP
D0 - D7
D0 - D7
D0 - D7
L/R VSS EIO1 EIO2
L/R EIO1 EIO2
L/R EIO1 EIO2
Y1 ---------------------->Y240 (data taking flow) first data
Y1 ---------------------->Y240
Y1 ---------------------->Y240
last data
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XCK
MD
MD
MD
FR
FR
FR
LP
LP
LP
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NT7704
5. Timing waveform of 4-Device cascade Connection of Segment Drivers
FR
LP
XCK
First data D0~D7 n12 device A EI (device A) n12 device B n12 device C n12 device D
Last data n12
H L
EO (device A)
EO (device B)
EO (device C) n: 4-bit parallel mode 60 8-bit parallel mode 30
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6. Connection Examples for Common Drivers
First Last
Y240
Y1
Y240
Y1
Y240
Y1
D
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
L/R
MD
L/R
MD
L/R
MD
CS
CS
CS
FR
FR
D7
D7
LP VSS (VDD) VSS VSS DISPOFF CS FR
LP
Single Mode (Shifting towards the left)
FR DISPOFF VDD VSS VSS (VDD) LP
MD
MD
D7
LP
LP
MD
D7
D7
D7
LP
LP
DISPOFF
DISPOFF
DISPOFF
L/R
L/R
D
EIO1
EIO2
EIO1
EIO2
EIO1
L/R
FR
FR
FR
EIO2
Y1
Y240
Y1
Y240
Y1
Y240
First
Last
Single Mode (Sifting towards the right)
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LP
FR
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NT7704
First1 Last1 First2 Last2
Y240
Y1
Y240
Y121 Y120
Y1
Y240
Y1
D1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF D7
EIO1
L/R
L/R
L/R
MD
MD
MD
FR
D7
D7
FR
LP D2 VSS (VDD) VDD VSS DISPOFF FR
Dual mode (Shifting towards the left)
FR DISPOFF VDD VDD VSS (VDD) D2 LP
MD
MD
D7
LP
LP
LP
DISPOFF
DISPOFF
DISPOFF
MD
D7
D7
LP
LP
L/R
L/R
D1
EIO1
EIO2
EIO1
EIO2
EIO1
L/R
FR
FR
FR
EIO2
Y1
Y240
Y1
Y120 Y121
Y240
Y1
Y240
First1
Last1 First2
Last2
Dual mode (Shifting towards the right)
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LP
FR
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NT7704
7. Precaution Be careful when connecting or disconnecting the power This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur if voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The details are as follows: ! When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. ! We recommend that you connect a serial resistor (50-100 ) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value of the resistor in consideration of LCD display grade. In addition, when connecting the logic power supply, the logic condition of the LSI inside is insecure. Therefore, connect the LCD driver power supply only after resetting the logic condition of this LSI inside to the DISPOFF function. After that, the DISPOFF cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver output pins to level V5 on the DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown.
VDD
VDD VSS VDD
DISPOFF
VSS V0
V0 VSS
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NT7704
Absolute Maximum Rating*
DC Supply Voltage VDD . . . . . . . . . . . . . -0.3V to +7.0V DC Supply Voltage V0 . . . . . . . . . . . . . . -0.3V to +30V Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Ambient Temperature . . . . -30C to +85C Storage Temperature . . . . . . . . . . . . .-45C to +125C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
DC Characteristics Segment Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85C, unless otherwise noted) Parameter Operating Voltage 1 Operating Voltage 2 Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1 Symbol VDD V0 VIH VIL VOH VOL IIH Min. 2.5 15 0.8 VDD VDD - 0.4 Typ. Max. 5.5 30 0.2 VDD +0.4 +1.0 Unit V V V V V V A A D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins EIO1, EIO2 pins, IOH = -0.4mA EIO1, EIO2 pins, IOL = +0.4mA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VDD D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VSS V0 = +30.0V k A mA mA mA V0 = +20.0V VSS pin, Note 1 VDD pin, Note 2 VDD pin, Note 3 V0 pin, Note 4 Y1 - Y240 pins, V O N = 0.5V Condition
Input leakage current 2
IIL
-
1.5 2.0 -
-1.0 2.0 2.5 10 2 12 1.5
Output resistance Stand-by current Consumed current (1) (Deselection) Consumed current (2) (Selection) Consumed current
RON ISB IDD1 IDD2 I0 -
Note: 1. VDD = +5.0V, V0 = +30V, VI = VSS 2. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load, EI = VDD The input data is turned over by the data taking clock (4-bit Parallel input mode) 3. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load. EI = VSS The input data is turned over by the data taking clock (4-bit parallel input mode) 4. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, fLP = 41.6kHz. fFR = 80 Hz, No-load The input data is turned over by the data taking clock (4-bit parallel-input mode)
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Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85C, unless otherwise noted) Parameter Operating Voltage Operating Voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1 Symbol VDD V0 VIH VIL VOH VOL IIH Min. 2.5 15 0.8 VDD VDD - 0.4 Typ. Max. 5.5 30 0.2 VDD +0.4 +1.0 Unit V V V V V V A A A k A A A D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins EIO1, EIO2 pins, IOH = -0.4mA EIO1, EIO2 pins, IOL = +0.4mA D0 - 6, LP, L/R, FR, MD, S/C and DISPOFF pins, VI = VDD D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VSS XCK, EIO1, EIO2, D7 pins V0 = +30.0V V0 = +20.0V VSS pin, Note 1 VDD pin, Note 2 V0 pin, Note 2 Y1 - Y240 pins, V O N = 0.5V Condition
Input leakage current 2 Input pull down current Output resistance Stand-by current Consumed current (1) Consumed current (2)
IIL IPD RON
-
1.5 2.0 -
-1.0 100 2.0 2.5 10 120 240
ISB IDD I0
-
Note: 1. VDD = +5.0V, V0 = +30.0V, VI = VSS 2. VDD = +5.0V, V0 = +30.0V, fLP = 41.6KHz, fFR = 80Hz, case of 1/480 duty operation, No-load
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AC Characteristics Segment Mode 1 (VSS = V5 = 0V, VDD = 4.5 - 5.5V, V0 = 15 to 30V, and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock rise time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 10 100 1.2 Min. 50 15 15 10 12 15 0 30 25 25 Typ. 30 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 10ns, Note 1
Note: 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-twckl)/2 is the maximum in the case of high speed operation.
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Segment Mode 2 (VSS = V5 = 0V, VDD = 3.0 - 4.5V, V0 = 15 to 30V, and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock fall time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 15 100 1.2 Min. 66 23 23 15 23 30 0 50 30 30 Typ. 41 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 10ns, Note 1
Note: 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-tWCKL)/2 is the maximum in the case of high speed operation.
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NT7704
Segment Mode 3 (VSS = V5 = 0V, VDD = 2.5 - 3.0V, V0 = 15 to 30V, and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock fall time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 15 100 1.2 Min. 82 28 28 20 23 30 0 65 30 30 Typ. 57 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 10ns, Note 1
Note: 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-tWCKL)/2 is the maximum in the case of high speed operation.
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NT7704
Timing waveform of the Segment Mode
tWLPH
LP
tLD tLS
tSL
tLH tWCKH
tWCKL
XCK
tr
tr tWCK
tDS
tDH
D0 - D7
LAST DATA
TOP DATA
tWDL
tSD
DISPOFF
LP
1 2 n
XCK
tS
EI
tD
EO
n: 4-bit parallel mode 60 8-bit parallel mode 30
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y240
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NT7704
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V and TA = -30 to +85C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Data setup time Data hole time Input signal rise time Input signal fall time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWLP tWLPH 30 tSU tH tr tf tSD tWDL tDL tpd1, tpd2 tpd3 100 1.2 30 50 50 50 200 1.2 1.2 ns ns ns ns ns ns s ns s s CL = 15pF CL = 15pF CL = 15pF VDD = +2.5 - +4.5V Min. 250 15 Typ. Max. Unit ns ns Condition tr, tf 20ns VDD = +5.0V 10%
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NT7704
Timing Characteristics of Common Mode
tWLP
LP
tr
tWLPH tSU
tf tH
EIO2 (DI7)
tDL
EIO1
tWDL
tSD
DISPOFF
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y240
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NT7704
Application Circuit (for reference only)
SEG960 SEG959
EIO1
Y1 - Y240
FR LP DISPOFF XCK
MD S/C L/R D0 - D7 EIO2 EIO1
Y1 - Y240
FR LP DISPOFF
MD S/C L/R D0 - D7 EIO2 EIO1
960*480 DOT MATRIX LCD PANEL
XCK
Y1 - Y240
FR LP DISPOFF XCK
MD S/C L/R D0 - D7 EIO2 EIO1
Y1 - Y240
SEG3 SEG2 SEG1 C O M 4 7 9 C O M 4 8 0
MD FR LP DISPOFF XCK S/C L/R D0 - D7 EIO2
C O M 1
C O M 2
C O M 3
Y1 - Y240
XCK
Y1 - Y240
DISPOFF
NT7704*2
D0 - D7
EIO1
EIO2
EIO1
D0 - D7
DISPOFF
EIO2
S/C
S/C
L/R
L/R
MD
MD
XCK
LP
FR
FR
LP
(case of 1/n bias)
V1 V0
V2
V3
V4
VSS V0 R R (n-4)R R R
DISPOFF
LCD controller
Note: V0-V1>1.5V
V5 VDD VSS
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XD0 - XD7
YD
XCK
FR
LP
NT7704*4
/8
/5 /5
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NT7704
Bonding Diagram
12968um
432 x
Y
225 x x
433
x
224
Dummy Pad
NT7704
448 x 1
ALK_L
(0,0)
X
1168um
209 x 208
x
ALK_R
Pad Location
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Designation V0L V0L V0L V0L V0L V0L V0L V0L V0L V0L V0L V0L V12L V12L V12L V12L V12L V12L V12L V12L V43L V43L V43L V43L V43L V43L V43L V43L V5L V5L X -6220 -6150 -6090 -6030 -5970 -5910 -5850 -5790 -5730 -5670 -5610 -5550 -5490 -5430 -5370 -5310 -5250 -5190 -5130 -5070 -5010 -4950 -4890 -4830 -4770 -4710 -4650 -4590 -4530 -4470 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 Pad No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Designation V5L V5L V5L V5L V5L V5L V5L V5L V5L V5L VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS X -4410 -4350 -4290 -4230 -4170 -4110 -4050 -3990 -3930 -3870 -3810 -3750 -3690 -3630 -3570 -3510 -3450 -3390 -3330 -3270 -3210 -3150 -3090 -3030 -2970 -2910 -2850 -2790 -2730 -2670 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521
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Pad Location (continued)
Pad No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD S/C S/C EIO2 EIO2 EIO2 D0 D0 D0 X -2610 -2550 -2490 -2430 -2370 -2310 -2250 -2190 -2130 -2070 -2010 -1950 -1890 -1830 -1770 -1710 -1650 -1590 -1530 -1470 -1410 -1350 -1290 -1230 -1170 -1110 -1050 -990 -930 -870 -810 -750 -690 -630 -570 -510 -450 -390 -330 -270 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 Designation D1 D1 D1 D2 D2 D2 D3 D3 D3 D4 D4 D4 D5 D5 D5 D6 D6 D6 D7 D7 D7 XCK XCK XCK DISPOFF DISPOFF DISPOFF LP LP LP EIO1 EIO1 EIO1 FR FR FR L/R L/R L/R MD X -210 -150 -90 -30 30 90 150 210 270 330 390 450 510 570 630 690 750 810 870 930 990 1050 1110 1170 1230 1290 1350 1410 1470 1530 1590 1650 1710 1770 1830 1890 1950 2010 2070 2130 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521
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Pad Location (continued)
Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Designation MD MD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS V5R V5R V5R V5R V5R V5R V5R V5R V5R V5R V5R V5R X 2190 2250 2310 2370 2430 2490 2550 2610 2670 2730 2790 2850 2910 2970 3030 3090 3150 3210 3270 3330 3390 3450 3510 3570 3630 3690 3750 3810 3870 3930 3990 4050 4110 4170 4230 4290 4350 4410 4470 4530 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 Pad No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 Designation V43R V43R V43R V43R V43R V43R V43R V43R V12R V12R V12R V12R V12R V12R V12R V12R V0R V0R V0R V0R V0R V0R V0R V0R V0R V0R V0R V0R Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 X 4590 4650 4710 4770 4830 4890 4950 5010 5070 5130 5190 5250 5310 5370 5430 5490 5550 5610 5670 5730 5790 5850 5910 5970 6030 6090 6150 6220 6430 6430 6430 6430 6430 6430 6430 6430 6430 6430 6430 6430 Y -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -521 -450 -390 -330 -270 -210 -150 -90 -30 30 90 150 210
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Pad Location (continued)
Pad No. 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 Designation Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 X 6430 6430 6430 6430 6210 6150 6090 6030 5970 5910 5850 5790 5730 5670 5610 5550 5490 5430 5370 5310 5250 5190 5130 5070 5010 4950 4890 4830 4770 4710 4650 4590 4530 4470 4410 4350 4290 4230 4170 4110 Y 270 330 390 450 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 Pad No. 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Designation Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 X 4050 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 Y 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529
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Pad Location (continued)
Pad No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 Designation Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 X 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 Y 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 Pad No. 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 Designation Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 Y161 Y162 Y163 Y164 Y165 Y166 Y167 Y168 Y169 Y170 Y171 Y172 X -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 Y 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529
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Pad Location (continued)
Pad No. 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 Designation Y173 Y174 Y175 Y176 Y177 Y178 Y179 Y180 Y181 Y182 Y183 Y184 Y185 Y186 Y187 Y188 Y189 Y190 Y191 Y192 Y193 Y194 Y195 Y196 Y197 Y198 Y199 Y200 Y201 Y202 Y203 Y204 Y205 Y206 Y207 X -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4410 -4470 -4530 -4590 -4650 -4710 -4770 -4830 -4890 -4950 -5010 -5070 -5130 -5190 Y 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 Pad No. 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 Designation Y208 Y209 Y210 Y211 Y212 Y213 Y214 Y215 Y216 Y217 Y218 Y219 Y220 Y221 Y222 Y223 Y224 Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240 ALK_L ALK_R X -5250 -5310 -5370 -5430 -5490 -5550 -5610 -5670 -5730 -5790 -5850 -5910 -5970 -6030 -6090 -6150 -6210 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6430 -6318 6318 Y 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 529 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -533 -533
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Dummy Pad Location (Total: 6 pin)
NO. 1 2 3 X 6430 6430 6280 Y -520 520 529 NO. 4 5 6 X -6280 -6430 -6430 Y 529 520 -520
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Package Information
A1 A2 D1 208m1n1 D2 D1 A1 A2
C1 n1 D1 D2 m1 n1 m2 n1 4n1m2 m3 m1 m2 D1 C1 H J B D1 C3 65m1n2 (L) D2 76m3n2 n2 m1 2m2n1
C2
C1 D1 D2
16n1m1 n1
r
NT7704
m2
r m3 m1 m1 n2 C3 D2 65m1n2 (R) D1 B H J m2
16n1m1 n1
D1 C1
Chip Outline Dimensions
Symbol A1 A2 B C1 C2 C3 D1 D2 Dimensions in um 204 54 264 64 55 63 70 60 Symbol H J m1 m2 m3 n1 n2 r Dimensions in um 51 166 39 55 38 72 90 35
unit: um
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TCP Pin Layout
DUMMY Y1 Y2 Y3 Y4 Y5 33 34 35 36 37
DUMMY 32 31 30 29 28 27 26 25 24 23 22 21 V0R V0R V12R V43R V5R NC VSS NC MD L/R FR EIO1 LP DISPOFF XCK D7 D6 D5 D4 D3 D2 D1 D0 EIO2 S/C VDD VSS V5L V43L V12L V0L V0L DUMMY
NT7704
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Y118 Y119 Y120 Y121 Y122 Y123
150 151 152 153 154 155
Y236 Y237 Y238 Y239 Y240 DUMMY
268 269 270 271 272
(COPPER SIDE VIEW)
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External View of TCP Pins
T H704 N T7
AB
F4
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NT7704
Cautions concerning storage: 1. When storing the product, it is recommended that it be left in its shipping package. After the seal of the packing bag has been broke, store the products in a nitrogen atmosphere. 2. Storage conditions : Storage state unopened (less than 90 days) After seal of broken (less than 30 days) Storage conditions Temperature: 5 to 30; humidity: 80%RH or less Room temperature, dry nitrogen atmosphere
3. Don't store in a location exposed to corrosive gas or excessive dust. 4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature. 5. Don't store the product such that it is subjected to an excessive load weight, such as by stacking. 6. Deterioration of the plating may occur after long-term storage, so special care is required. It is recommended that the products be inspected before use.
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Tray Information
f
Y
e
c
W1
W2
T2
T1
X
X
d
Y
g h
W1 W2 a g h T2 T1 b e
f
SECTION X-X
Tray Outline Dimensions
Symbol a b c d e f Dimensions in mm 1.30 2.67 13.30 16.26 1.60 1.40 Symbol g h W1 W2 T1 T2 Dimensions in mm 0.64 4.20 76.0 68.0 71.0 68.3
SECTION Y-Y
H30-52359-25
425=100
unit: mm
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NT7704
Ordering Information
Part No. NT7704H-BDT NT7704H-TABF4 Package Au bump on chip tray TCP Form
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NT7704
Product Spec. Change Notice
NT7704 Specification Revision History Version 1.0 0.2 0.1 0.0 Content TCP and tray information addition (Page 36-39) Gold Bump Size revision (Page 34) m1: 45 39, m2: 58 55 Pad Location Addition Original Date Dec. 2001 Sep. 2001 Nov. 2000 Nov. 2000
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